--
-- VHDL Architecture codec_control2.int_to_vector.arch
--
-- Created:
--          by - toban963.student (southfork-11.edu.isy.liu.se)
--          at - 13:40:19 10/13/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY int_to_vector IS
   PORT( 
      mono_sample : IN     integer;
      DA_right_in : OUT    std_logic_vector (23 DOWNTO 0)
   );

-- Declarations

END int_to_vector ;

--
ARCHITECTURE arch OF int_to_vector IS
BEGIN
  DA_right_in <= std_logic_vector(to_signed(mono_sample, 24));
END ARCHITECTURE arch;

